\doxysection{LTDC\+\_\+\+Layer\+\_\+\+Type\+Def Struct Reference}
\hypertarget{struct_l_t_d_c___layer___type_def}{}\label{struct_l_t_d_c___layer___type_def}\index{LTDC\_Layer\_TypeDef@{LTDC\_Layer\_TypeDef}}


LCD-\/\+TFT Display layer x Controller.  




{\ttfamily \#include $<$stm32h723xx.\+h$>$}

\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_l_t_d_c___layer___type_def_a3f9827b30a402fd3d85fe4f4b8eb49c9}{CR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_l_t_d_c___layer___type_def_a9c72a83598a0ee20148f01a486f54ac0}{WHPCR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_l_t_d_c___layer___type_def_aa3238d4c30b3ec500b2007bc061020db}{WVPCR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_l_t_d_c___layer___type_def_a1037f0255519c1c6c14af5b17a4de3ca}{CKCR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_l_t_d_c___layer___type_def_a401b8bbdd7d666b112a747b1a6d163ae}{PFCR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_l_t_d_c___layer___type_def_af3708f47198ca52e0149584a8c382362}{CACR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_l_t_d_c___layer___type_def_aaedb1dc65cb10a98f4c53f162b19bb39}{DCCR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_l_t_d_c___layer___type_def_ad597faecb079859e9cdb849c8cf78aec}{BFCR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_l_t_d_c___layer___type_def_a69d1bd327c7b02f9a1c9372992939406}{RESERVED0}} \mbox{[}2\mbox{]}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_l_t_d_c___layer___type_def_aa79c0c2be9b6f8e4f034d8d5fe8e9345}{CFBAR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_l_t_d_c___layer___type_def_ae4673c5b4a2df7b770d82e43b1806ccf}{CFBLR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_l_t_d_c___layer___type_def_adbd3ad2a70d1578d630acfdb9a526320}{CFBLNR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_l_t_d_c___layer___type_def_ad08bb6a4577311f9dfcc7a3a15f0c7c9}{RESERVED1}} \mbox{[}3\mbox{]}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_l_t_d_c___layer___type_def_ae4ce84d11912847542fcdc03ae337176}{CLUTWR}}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
LCD-\/\+TFT Display layer x Controller. 

\label{doc-variable-members}
\Hypertarget{struct_l_t_d_c___layer___type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_l_t_d_c___layer___type_def_ad597faecb079859e9cdb849c8cf78aec}\index{LTDC\_Layer\_TypeDef@{LTDC\_Layer\_TypeDef}!BFCR@{BFCR}}
\index{BFCR@{BFCR}!LTDC\_Layer\_TypeDef@{LTDC\_Layer\_TypeDef}}
\doxysubsubsection{\texorpdfstring{BFCR}{BFCR}}
{\footnotesize\ttfamily \label{struct_l_t_d_c___layer___type_def_ad597faecb079859e9cdb849c8cf78aec} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t LTDC\+\_\+\+Layer\+\_\+\+Type\+Def\+::\+BFCR}

LTDC Layerx Blending Factors Configuration Register Address offset\+: 0x\+A0 \Hypertarget{struct_l_t_d_c___layer___type_def_af3708f47198ca52e0149584a8c382362}\index{LTDC\_Layer\_TypeDef@{LTDC\_Layer\_TypeDef}!CACR@{CACR}}
\index{CACR@{CACR}!LTDC\_Layer\_TypeDef@{LTDC\_Layer\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CACR}{CACR}}
{\footnotesize\ttfamily \label{struct_l_t_d_c___layer___type_def_af3708f47198ca52e0149584a8c382362} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t LTDC\+\_\+\+Layer\+\_\+\+Type\+Def\+::\+CACR}

LTDC Layerx Constant Alpha Configuration Register Address offset\+: 0x98 \Hypertarget{struct_l_t_d_c___layer___type_def_aa79c0c2be9b6f8e4f034d8d5fe8e9345}\index{LTDC\_Layer\_TypeDef@{LTDC\_Layer\_TypeDef}!CFBAR@{CFBAR}}
\index{CFBAR@{CFBAR}!LTDC\_Layer\_TypeDef@{LTDC\_Layer\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CFBAR}{CFBAR}}
{\footnotesize\ttfamily \label{struct_l_t_d_c___layer___type_def_aa79c0c2be9b6f8e4f034d8d5fe8e9345} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t LTDC\+\_\+\+Layer\+\_\+\+Type\+Def\+::\+CFBAR}

LTDC Layerx Color Frame Buffer Address Register Address offset\+: 0x\+AC \Hypertarget{struct_l_t_d_c___layer___type_def_adbd3ad2a70d1578d630acfdb9a526320}\index{LTDC\_Layer\_TypeDef@{LTDC\_Layer\_TypeDef}!CFBLNR@{CFBLNR}}
\index{CFBLNR@{CFBLNR}!LTDC\_Layer\_TypeDef@{LTDC\_Layer\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CFBLNR}{CFBLNR}}
{\footnotesize\ttfamily \label{struct_l_t_d_c___layer___type_def_adbd3ad2a70d1578d630acfdb9a526320} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t LTDC\+\_\+\+Layer\+\_\+\+Type\+Def\+::\+CFBLNR}

LTDC Layerx Color\+Frame Buffer Line Number Register Address offset\+: 0x\+B4 \Hypertarget{struct_l_t_d_c___layer___type_def_ae4673c5b4a2df7b770d82e43b1806ccf}\index{LTDC\_Layer\_TypeDef@{LTDC\_Layer\_TypeDef}!CFBLR@{CFBLR}}
\index{CFBLR@{CFBLR}!LTDC\_Layer\_TypeDef@{LTDC\_Layer\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CFBLR}{CFBLR}}
{\footnotesize\ttfamily \label{struct_l_t_d_c___layer___type_def_ae4673c5b4a2df7b770d82e43b1806ccf} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t LTDC\+\_\+\+Layer\+\_\+\+Type\+Def\+::\+CFBLR}

LTDC Layerx Color Frame Buffer Length Register Address offset\+: 0x\+B0 \Hypertarget{struct_l_t_d_c___layer___type_def_a1037f0255519c1c6c14af5b17a4de3ca}\index{LTDC\_Layer\_TypeDef@{LTDC\_Layer\_TypeDef}!CKCR@{CKCR}}
\index{CKCR@{CKCR}!LTDC\_Layer\_TypeDef@{LTDC\_Layer\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CKCR}{CKCR}}
{\footnotesize\ttfamily \label{struct_l_t_d_c___layer___type_def_a1037f0255519c1c6c14af5b17a4de3ca} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t LTDC\+\_\+\+Layer\+\_\+\+Type\+Def\+::\+CKCR}

LTDC Layerx Color Keying Configuration Register Address offset\+: 0x90 \Hypertarget{struct_l_t_d_c___layer___type_def_ae4ce84d11912847542fcdc03ae337176}\index{LTDC\_Layer\_TypeDef@{LTDC\_Layer\_TypeDef}!CLUTWR@{CLUTWR}}
\index{CLUTWR@{CLUTWR}!LTDC\_Layer\_TypeDef@{LTDC\_Layer\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CLUTWR}{CLUTWR}}
{\footnotesize\ttfamily \label{struct_l_t_d_c___layer___type_def_ae4ce84d11912847542fcdc03ae337176} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t LTDC\+\_\+\+Layer\+\_\+\+Type\+Def\+::\+CLUTWR}

LTDC Layerx CLUT Write Register Address offset\+: 0x144 \Hypertarget{struct_l_t_d_c___layer___type_def_a3f9827b30a402fd3d85fe4f4b8eb49c9}\index{LTDC\_Layer\_TypeDef@{LTDC\_Layer\_TypeDef}!CR@{CR}}
\index{CR@{CR}!LTDC\_Layer\_TypeDef@{LTDC\_Layer\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CR}{CR}}
{\footnotesize\ttfamily \label{struct_l_t_d_c___layer___type_def_a3f9827b30a402fd3d85fe4f4b8eb49c9} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t LTDC\+\_\+\+Layer\+\_\+\+Type\+Def\+::\+CR}

LTDC Layerx Control Register Address offset\+: 0x84 \Hypertarget{struct_l_t_d_c___layer___type_def_aaedb1dc65cb10a98f4c53f162b19bb39}\index{LTDC\_Layer\_TypeDef@{LTDC\_Layer\_TypeDef}!DCCR@{DCCR}}
\index{DCCR@{DCCR}!LTDC\_Layer\_TypeDef@{LTDC\_Layer\_TypeDef}}
\doxysubsubsection{\texorpdfstring{DCCR}{DCCR}}
{\footnotesize\ttfamily \label{struct_l_t_d_c___layer___type_def_aaedb1dc65cb10a98f4c53f162b19bb39} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t LTDC\+\_\+\+Layer\+\_\+\+Type\+Def\+::\+DCCR}

LTDC Layerx Default Color Configuration Register Address offset\+: 0x9C \Hypertarget{struct_l_t_d_c___layer___type_def_a401b8bbdd7d666b112a747b1a6d163ae}\index{LTDC\_Layer\_TypeDef@{LTDC\_Layer\_TypeDef}!PFCR@{PFCR}}
\index{PFCR@{PFCR}!LTDC\_Layer\_TypeDef@{LTDC\_Layer\_TypeDef}}
\doxysubsubsection{\texorpdfstring{PFCR}{PFCR}}
{\footnotesize\ttfamily \label{struct_l_t_d_c___layer___type_def_a401b8bbdd7d666b112a747b1a6d163ae} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t LTDC\+\_\+\+Layer\+\_\+\+Type\+Def\+::\+PFCR}

LTDC Layerx Pixel Format Configuration Register Address offset\+: 0x94 \Hypertarget{struct_l_t_d_c___layer___type_def_a69d1bd327c7b02f9a1c9372992939406}\index{LTDC\_Layer\_TypeDef@{LTDC\_Layer\_TypeDef}!RESERVED0@{RESERVED0}}
\index{RESERVED0@{RESERVED0}!LTDC\_Layer\_TypeDef@{LTDC\_Layer\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED0}{RESERVED0}}
{\footnotesize\ttfamily \label{struct_l_t_d_c___layer___type_def_a69d1bd327c7b02f9a1c9372992939406} 
uint32\+\_\+t LTDC\+\_\+\+Layer\+\_\+\+Type\+Def\+::\+RESERVED0\mbox{[}2\mbox{]}}

Reserved \Hypertarget{struct_l_t_d_c___layer___type_def_ad08bb6a4577311f9dfcc7a3a15f0c7c9}\index{LTDC\_Layer\_TypeDef@{LTDC\_Layer\_TypeDef}!RESERVED1@{RESERVED1}}
\index{RESERVED1@{RESERVED1}!LTDC\_Layer\_TypeDef@{LTDC\_Layer\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED1}{RESERVED1}}
{\footnotesize\ttfamily \label{struct_l_t_d_c___layer___type_def_ad08bb6a4577311f9dfcc7a3a15f0c7c9} 
uint32\+\_\+t LTDC\+\_\+\+Layer\+\_\+\+Type\+Def\+::\+RESERVED1\mbox{[}3\mbox{]}}

Reserved \Hypertarget{struct_l_t_d_c___layer___type_def_a9c72a83598a0ee20148f01a486f54ac0}\index{LTDC\_Layer\_TypeDef@{LTDC\_Layer\_TypeDef}!WHPCR@{WHPCR}}
\index{WHPCR@{WHPCR}!LTDC\_Layer\_TypeDef@{LTDC\_Layer\_TypeDef}}
\doxysubsubsection{\texorpdfstring{WHPCR}{WHPCR}}
{\footnotesize\ttfamily \label{struct_l_t_d_c___layer___type_def_a9c72a83598a0ee20148f01a486f54ac0} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t LTDC\+\_\+\+Layer\+\_\+\+Type\+Def\+::\+WHPCR}

LTDC Layerx Window Horizontal Position Configuration Register Address offset\+: 0x88 \Hypertarget{struct_l_t_d_c___layer___type_def_aa3238d4c30b3ec500b2007bc061020db}\index{LTDC\_Layer\_TypeDef@{LTDC\_Layer\_TypeDef}!WVPCR@{WVPCR}}
\index{WVPCR@{WVPCR}!LTDC\_Layer\_TypeDef@{LTDC\_Layer\_TypeDef}}
\doxysubsubsection{\texorpdfstring{WVPCR}{WVPCR}}
{\footnotesize\ttfamily \label{struct_l_t_d_c___layer___type_def_aa3238d4c30b3ec500b2007bc061020db} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t LTDC\+\_\+\+Layer\+\_\+\+Type\+Def\+::\+WVPCR}

LTDC Layerx Window Vertical Position Configuration Register Address offset\+: 0x8C 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Device/\+ST/\+STM32\+H7xx/\+Include/\mbox{\hyperlink{stm32h723xx_8h}{stm32h723xx.\+h}}\end{DoxyCompactItemize}
